1. Field of the Invention
The present invention relates to the field of hardware design and, more particularly, to generating a hardware description from a general-purpose, high level programming language.
2. Description of the Related Art
The design of field programmable gate arrays (FPGAS) or application specific integrated circuits (ASICs) typically begins with the development and validation of an algorithm which the integrated circuit (IC) is intended to implement. Presently, developers validate algorithmic designs by implementing algorithms in a high level programming language such as C, C++, Java, or the like. High level programming languages provide designers with the ability to rapidly prototype an algorithm, explore the algorithm in further detail, and ultimately prove or validate that the algorithm can sufficiently process the data for which the algorithm and the IC are being developed.
Once an algorithm has been validated, the designer can begin the process of transforming the high level language design into a hardware description implementation using VERILOG, VHDL, or some other hardware description language alternative. Presently, this transformation is performed manually by designers. As a result, the process can be very time intensive and error prone. Transformation of a high level language design to a hardware description language implementation involves tracking an extraordinary number of inter-relationships between timing signals and data. The designer must think in terms of clock cycles and relative timing between signals in the hardware description language. State machines must be designed that are capable of correctly moving data through the hardware description language code, and which are capable of enabling the correct subsystems at the proper times.
Attempts have been made to develop improved tools to aid in the transition from a high level language design to a hardware description language design. For example, specialized programming languages such as Handel-C and SystemC are enhanced programming languages that, when compiled, can produce a hardware description conforming to a particular hardware description language specification such as VERILOG or VHDL. Specialized programming languages such as these, however, are “hardware aware” in that the languages include significant enhancements in the way of standard libraries and extensions which allow programs written in these languages to be compiled into suitable hardware descriptions.
Handel-C, SystemC, and other “hardware aware” languages use a technique known as progressive elaboration. Under the technique of progressive elaboration, a designer codes a design in a high level language. After initial algorithmic verification, the designer successively adds more information and/or hardware aware constructs to the code to direct the compiler in terms of implementation. A final design is achieved by adding sufficient information to the source code to generate the desired results.
While “hardware aware” languages do help to ease the translation of validated algorithms to hardware description language designs, there are disadvantages to the use of specialized languages. One such disadvantage is the time required for developers to familiarize themselves with a different special purpose language. Although “hardware aware” languages typically are rooted in a known high level language such as the C programming language, developers still must learn special enhancements and additions to the language which make the generation of a hardware description language output possible.
Another disadvantage of specialized “hardware aware” languages can be the cost associated with purchasing the language as a design tool. The acquisition of a specialized language as a design tool adds yet another expense to the IC development process. Finally, “hardware aware” design tools which rely upon progressive elaboration design techniques require source code modifications to work properly.
Accordingly, a need exists in the electronics industry for an efficient way of capturing design functionality in a more abstract manner than is presently available with conventional hardware description languages.